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Max Vee current allowed on CFAG160160B series?

ahooton

New member
On the CFAG160160B* modules: What the maximum current allowed on Vee?

Crystalfontz: I would have expected this to be in the datasheet, but it's not. It would be *very* helpful if full electrical specifications are provided in the datasheets for products that are intended to be integrated into OEM systems, including max currents on all pins. Instead of a manual potentiometer for lcd bias, I'm using Vee in a design utilizing a PWM-driven RC circuit that drives a transistor to mix my onboard +5v and Vee -15v potentials for the lcd bias. However, I need to know the current limits allowable through Vee in order to successfully design this circuit.

Thanks,
Al
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CF Tech

Administrator
The Vee is only intended to drive the manual potentiometer, so we do not fully specify it as a power supply.

The response by cosmicvoid in this thread:

https://forum.crystalfontz.com/showthread.php?t=5578

sounds reasonable to me. Is it not holding up at 15mA? Do you need more than 15mA?

We can probably get a schematic of the NV circuit for you, but we would have to do that in a support ticket.
 

ahooton

New member
Wow, that's embarrassing -- the answer was already right there, in a thread I had started, no less... :rolleyes: That's what happens when I get back to work on a side project after several months have gone by. Sorry about that. However, after a lot more investigation today, it appears there is still a problem to be resolved with the CFAG160160B modules.

A few days ago I discovered Vee blown on a module that has been in one of our engineering prototypes for several weeks, working fine. Nobody had stuck their hands in it, nothing had been changed, etc. One day Vee was there, the next day it was blown. We had simply been powering up our prototype, flashing code to the processor on our board, running the code (which resets the lcd module when it starts), and eventually powering it down.

With my investigation today, I believe I have tracked the blown Vee down to Vo (pin 4) drawing too much current after these CFAG160160B modules are powered up but *prior* to the module being initialized by dropping/raising the reset line (pin 10).

While 15mA capacity on Vee is plenty, more than enough, this is only true as long as Vo doesn't decide to draw more current than it should. The typical current on Vo is not actually given in the datasheet, at least not that I see, but let's call it Ivo.

My measurements today show that after the module is powered-up, then initialized, and everything is running correctly, Ivo is somewhere between 2-3mA, typically around 2.75mA when the bias is set so the screen is readable at room temperature. Running Vee through my PWM-controlled circuit to control Vo, I see a max of about 4mA pulled through Vee. So far, so good, I'm well below the 15mA max current through Vee.

However, when I power up the module but do not run the code on my processor, the reset line is never de-asserted/asserted to reset the module. In this state, Ivo is 17-18mA! Because of the load Vo is presenting, the current drawn from Vee is between 19-20mA. If I take a long time between power-up and resetting the module (for instance to flash new code, set breakpoints, pre-set some memory contents on the board, or other things related to using the prototype for firmware development) then Vee will eventually get blown because Vo is asking it to source too much current the entire time the module is powered up but not externally reset.

I put together a quick test on a breadboard using the potentiometer-based bias control approach shown in the data sheet, with the values shown. The same thing happens: After the module is powered up, but before it is reset, Vo is drawing so much current that it causes Vee to source well above 15mA through the simple potentiometer-based circuit.

So: From my perspective, I would see this as a design issue with the CFAG160160B modules. They should not power up in a state that causes them to operate outside of their own acceptable parameters prior to some external circuit de-asserting/asserting the reset line on pin 10. It might be a long time before an external circuit can get around to doing that (especially if it's software controlled). I realize there can be other perspectives on this, but I don't think this type of product should risk damaging itself in this way. Nor should it place the burden of avoiding damage on the external circuit designer, just because it doesn't power itself up to a sane operating state.

Not sure what I'm going to do at this point, unfortunately. Our hardware design is supposed to be locked down now. I guess I'm going to have to figure out some way to keep Vo disconnected from the circuit until after the processor has reset the module, if I can get the change incorporated and turn the board one more time.

CF Tech and cosmicvoid, I appreciate you both jumping in on this over the holiday. All further thoughts are appreciated, especially if you disagree with my characterization of this as a design issue with the modules. Other than this problem, we have been extremely happy with these modules and continue to drive towards commercializing a product that incorporates them (in a side-project kind of a way...).

Thanks!
 
It does seem unfortunate that the CFAG160 behaves this way, and not being privy to the internal design, I cannot comment whether this is normal or not. Does this occur on all of your display samples?

I can make one suggestion: insert a series resistor to the Vo connection, such that under worst case conditions the Vee current is limited to 10 mA. You may have to adjust your contrast circuit setting to compensate for the additional voltage drop, or put the resistor inside the feedback loop of your Vo generator circuit.

Maybe during product development, you could arrange to keep the display powered down until the code is ready to execute, or temporarily tack on a crude reset generator to give a reset at power-up. If you are willing to reveal more about your Vo generator circuit, I am willing to give more suggestions.
 

ahooton

New member
Thanks for the reply, cosmicvoid :

It does seem unfortunate that the CFAG160 behaves this way, and not being privy to the internal design, I cannot comment whether this is normal or not. Does this occur on all of your display samples?


I've tried it on four different units, and I'm getting identical behavior, so I'm pretty sure it's consistent.

I can make one suggestion: insert a series resistor to the Vo connection, such that under worst case conditions the Vee current is limited to 10 mA. You may have to adjust your contrast circuit setting to compensate for the additional voltage drop, or put the resistor inside the feedback loop of your Vo generator circuit.

Yeah, I've been playing with this over the last couple of hours. Unfortunately, anything I can think of that gets me to an acceptable pre-reset draw through Vee causes too much voltage drop during normal operation. The Vo control circuit is pretty simple, I've attached a schematic of it. PWMbias is an adjustable duty-cycle 0-5v signal, LCDneg16v is Vee, and Vneg-bias is Vo. At this point I don't believe there's a current-limit approach that will work without causing too much Vdrop, so I'm starting to think about ways to keep Vo and/or Vee disconnected until after the process is up off the ground and has reset the lcd module. PITA, and is going to add expense.

Maybe during product development, you could arrange to keep the display powered down until the code is ready to execute, or temporarily tack on a crude reset generator to give a reset at power-up. If you are willing to reveal more about your Vo generator circuit, I am willing to give more suggestions.

Unfortunately, if the board isn't powered up, there's no getting code into the processor, etc.

The crude reset generator is a possibility, I suppose. I'd really like to get this resolved more correctly, however. The idea of production systems in the field driving Vee to an overcurrent condition even for only a second or two before the processor can reset the lcd module bothers me, since the board will likely be powered up/down a number of times each working day. I'm somewhat concerned about the cumulative damage caused by those short overcurrent events.

Thanks!
 

Attachments

To isolate Vee from your bias circuit would need 2 fets/bjts and 2 resistors, not to mention an I/O pin (or other signal source) to enable it at the desired time (assuming a logic level enable signal). Less than thirty cents in parts, plus a little pcb real estate, and a few extra lines of code. A little clunky, perhaps.

You could put a pulldown resistor on the LCD reset input, so it would immediately be reset at power up (unless your cpu I/O pin defaulted to 'output' at a 1 state). Or you could connect the LCD reset input to the cpu reset line (assuming it would be asserted low at power up).

Or you could add a separate reset supervisor IC to the LCD reset, but then you'd have to use an I/O pin to sense when it had finished asserting its output before you could proceed with LCD init. Fifty cents and very little real estate.

Sorry I can't think of a magic bullet solution to your situation.
 
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