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CFAG12864B Timing


New member

Few quick questions...in the data sheet, page 9, the MPU Write Timing diagram shows the "Enable" bit is high before anything else is changed. Then the "E" bit is taken low, the other bits are manipulated, "E" is taken high again, data is moved to DB0-DB7, then "E" is taken low again. I might have missed it in the data sheet, but should I leave the E bit always high? (except when starting the E-cycle obviously) Must the E-cycle have the 3 edges (high-low, low-high, high-low) to properly function - ie enable the read/write operation? I have not played with graphics displays before but with the char displays (HD44780 compat) the E bit functioned simply with a low-high, high-low pulse (with the correct pulse width of course).

If I leave the E bit low and since there is no max limit on E-cycle width or E low level width, as long as I meet the spec (450nS) for E high level width shouldn't this be acceptable?

Sorry if the questions seem dumb, just trying to get it straight. Thanks.

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Think of E as the data strobe. Without it, nothing happens. Normally E will sit low, but you cannot leave it low (or high). I don't know why the data sheet shows it starting high, that's misleading. I suppose its just to illustrate the cycle width timing. If you ignore the initial high state of E in the diagram, it will make more sense.

For writing, the action occurs on the falling edge of E. So your data on the bus must be stable before you drop E.

For reading, the display will put data on the bus when E is high. So you should read the bus before dropping E.

E functions the same here as in the HD44780 type controllers.