CFAG12864B: Status Read and CS1, CS2?


New member
I have a CFAG12864B-TMI-V display.

When doing a "Status Read" do you have to specify which Segment Driver to read status from, by asserting CS1 or CS2 (logic 0), or should they both be left un-asserted (logic 1)?

If a CS does have to be asserted when doing a "Status Read", could they both be asserted during the same cycle, or would this cause bus-contention?

Thank you,

Nathaniel Hannigan
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I will start by saying "I don't know", but the data sheet shows the two segment controllers sharing the data bus. So I'd be willing to bet that the two chip selects cannot be asserted simultaneously for reading. But you'd have to assert at least one of them or you'll get no data (status). So you should assert the chip select for the half that you are wanting to write to.

How fast is your cpu? If its got a cycle time of 250 nS or longer, you may not even need to poll for busy status. Just put a NOP or two in the control routines to stretch the E width to minimum spec.

I expect you could use both chip selects for writing. This would allow you to clear the display in half the time of a single controller display.


New member
Thanks for the reply.

I'm using an FPGA and VHDL language to implement the controller as a hierarchical state machine. I have since got the design working, I just wasn't completely sure how the chip selects should be asserted for a "Status Read" since it isn't specified directly in the data sheet.