CFA533 Interfacing with FPGA


New member
I am trying to interface my CFA533 (RS232) with my board which already have an FPGA.

But while starting, I got stuck using Wintest633 with my module. Can somebody help?
I am not quite sure about the CRC generating algorithm to be implemented in FPGA.
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New member
Unable to run wintest_633

Thanks. I now understand how to generate the CRC for each packets.
But I am still unable to run the wintest_633 .
I connected three pins of CFA533-YYH-KL ( J_RS232) namely, TX, RX and GND to the DB9 connector of my PC.
I have given Power through PC Floppy Disk. JP13 is open and JP8 is short.
I still get the message at my wintest_633 "Looking for module...."

CF Tech

Do you have a "KS" (correct for talking to a PC) or a "KL" (correct for talking to logic-level devices like an FPGA)?

If U6 is loaded (lower left IC in this image), it is a KS and should talk to the PC:

If U6 is open, and the two jumpers under U6 are closed, it is a KL:



New member
The device which I have is CFA533 YYH KL.
So, according to you, it can not be connected to a PC. And thanks for the suggestion.

Next, plz tell me if I am wrong in my understanding.
1. When I try to connect it to my FPGA, the only lines to be connected are RX, TX, +5V and GND.
2. Short JP13. Do not Care for JP8.
3. I still have to design my RS232 controller on FPGA. Before I design that, if a reference timing diagram can be suggested, it will help me to quickly have my design ready.
4. Please suggest if I can still use the packet debugger of wintest_633 to generate the packets and CRC for my customized design.
Thanks in advance.

CF Tech

You could ask support for one of the USB adapters that was used on the older CFA-633. That would allow windows to generate the same signals that your FPGA needs to generate in order to talk to the logic-level CFA-533.

You can see the board on the left of this image:

As far as the byte timing it is standard RS-232 8 data 1 stop bit, no parity for whatever baud you want.

Once you get bytes out, you just need to assemble packets with the CRC. The simplest examples are probably here:


New member
Logic Level @ 3.3V

Thanks for the references.
I generated the same signals for the CFA533 as given in the references.
The only difference is that my FPGA generates the signal at 3.3V instead of 5V which is recommended. Can you please comment whether 3.3V will work for the CFA533?